An integrated circuit memory, such as a static random access memory (SRAM), is generally implemented as an array of memory cells in a plurality of rows and columns. A synchronous SRAM memory receives a clock signal for controlling the timing of the memory, and the speed of a synchronous memory is fixed by the clock frequency. Synchronous memories are often used as data caches for microprocessors. A data cache increases the performance of the microprocessor by storing data the microprocessor is most likely to use, in a relatively small, very fast memory array. In data caches, very fast, high frequency operation is essential. Therefore, data caches today are being designed with synchronous SRAMs using BICMOS technology. A BICMOS circuit combines bipolar transistors with CMOS (complementary metal-oxide-semiconductor) transistors on the same integrated circuit. Generally, bipolar transistors provide the advantage of high speed and high drive capability, while CMOS transistors provide the advantage of reduced power consumption.
During a read cycle of a synchronous memory, a pair of complementary bit lines communicate a data bit as a differential voltage to a first sense amplifier. The first sense amplifier detects and amplifies the relatively small differential voltage and communicates it to the data output stages of the memory by way of read global data lines. The read global data lines provide the data to a multiplexer and a clock controlled latch, where it is directed to another sense amplifier, sometimes called a final sense amplifier. A level converter then converts the data provided by the final sense amplifier to CMOS logic levels, and a clock controlled CMOS latch temporarily holds the data for timing purposes. The data is then level converted again, if other than a CMOS level output signal is desired. Finally, an output buffer having high drive capability receives the data from the level converter and provides it as a single-ended data signal to a data output pad.
The clock controlled latch circuit of a synchronous memory is generally implemented utilizing CMOS transistors because of their relatively low power consumption. However, CMOS logic circuits are too slow for applications requiring high speed, such as today's high performance workstations. Also, the additional gate delay caused by performing logic level conversions to and from CMOS logic levels further reduces the cycle time, as well as requiring additional area on the integrated circuit. In contrast to CMOS logic circuits, BICMOS logic circuits provide high speed operation for applications such as workstations, but consume too much power for some applications, such as battery powered computers.